1. Field of the Invention
The present invention is related to the field of semiconductor wafer processing, and more specifically to methods for cost effective singulation of integrated circuit dies from a semiconductor substrate, and devices made according to such methods.
2. Description of the Related Art
Semiconductor processing generally comprises multiple photolithographic, etching, plating and doping operations to form an array of individual integrated circuit dies on the surface of a semiconductor substrate, such as a wafer. For application of Radio Frequency Identification (RFID) tag chips, integrated circuit die densities frequently range in the tens of thousands of dies per wafer. Each die is separated from the others by a narrow inactive boundary referred to as a die “street”. Once integrated circuit die fabrication and testing at the wafer level are completed, the individual die is “singulated”. Singulation is typically accomplished by cutting along the die streets using a sawing process. With current practice, width of the street is about 60 microns. If the active area on a die is 250,000 square microns (500 microns on each side), then the total area of the die, including the 60 micron wide street around each die is 313,600 square microns. If a narrower, 20 micron wide street is used around the die, then the total die area becomes 270,400 square microns. The difference between a 60 micron wide street and a 20 micron wide street provides approximately 16% more dies per wafer. As die sizes decrease, it is imperative to reduce the width of die streets.
Current techniques involve thinning the wafer prior to sawing through the wafer, to complete the singulation.
What is needed is a method for die singulation which overcomes these limitations of the prior art.